The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of the IC evolution, functional density (defined as the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. A scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. But, such scaling down has increased the complexity of processing and manufacturing ICs. For these advances to be realized, similar developments in IC manufacturing are needed.
For example, as the semiconductor IC industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design have resulted in the development of three-dimensional (3D) devices. In the three-dimensional (3D) device, various interlayer connecting structures, such as contacts and through vias, are used to connect transistors and other devices. Currently, because copper offers lower resistivity than aluminum, and using a lower resistivity connecting material can decrease RC delay of the interlayer connecting structures, and thus increasing the device speed, copper has been used as a material for fabricating the interlayer connecting structures.